The present invention relates generally to storage devices and, more particularly, to test mode circuitry for electronic storage devices and the like.
An electronic storage device, such as a static random access memory (SRAM) device, is typically a monolithic device having both control and memory array circuitry. The control circuitry typically includes circuitry for testing the electronic storage device after it has been manufactured. Such test circuitry typically places the electronic storage device into a test mode wherein the different functions of the electronic storage device can be tested over a wide range of predetermined measurement conditions.
The test circuitry typically places the electronic storage device into the test mode whenever a high voltage, or supervoltage, is applied to one of the input pins of the electronic storage device. For example, the supervoltage can be applied to an input pin that is used as an address pin or a control pin during normal operation. The test circuitry detects the supervoltage on the input pin and places the electronic storage device into the test mode.
The test circuitry typically contains a high voltage detection circuit for detecting the supervoltage on the input pin. For example, referring to FIG. 1, there is shown a prior art high voltage detection circuit 10 for detecting a supervoltage on an input pin 12. The high voltage detection circuit 10 includes a diode stack 14, a weak load transistor (i.e., a transistor that is biased and/or dimensioned so as to conduct only a relatively small amount of current) 16, and a series of inverters 18. If no supervoltage is applied to input pin 12, the diodes in the diode stack 14 typically cannot become forward biased and the weak load transistor 16 maintains node N1 in a low state. The signal at node N1 is then buffered through the series of inverters 18 so as to cause the output signal HVOUT to be in an inactive low state. However, if a supervoltage is applied to input pin 12, the diodes in the diode stack 14 can become forward biased and node N1 can be brought to a high state. The signal at node N1 is then buffered through the series of inverters 18 so as to cause the output signal HVOUT to be brought to an active high state. When the output signal HVOUT is active high, the rest of the test circuitry (not shown) places the electronic storage device into the test mode.
There are problems associated with the above-described high voltage detection circuit 10. For example, because input pin 12 is connected to a source/drain junction of the diode stack 14, pin leakage can become an issue and the source/drain junction can become forward biased. Also, the numerous diodes in the diode stack 14 are very process sensitive. Thus, accidental entry into or exit from the test mode is possible at some process corners. In fact, this is even likely since, as previously indicated, the electronic storage device is tested over a wide range of predetermined measurement conditions. Further, a current path can exist on some process/voltage corners for the supply voltage. That is, at high VCC (hot temperature) and a minimum transistor threshold corner, node N1 may not be at ground and the transistors in the first inverter in the series of inverters 18 may have some crowbar current. Additionally, the entire circuit is latch-up sensitive due to the range of voltages over which node N1 can reside.
In addition to the above-stated problems, the electronic storage device may not be thoroughly, or at least efficiently, tested due to limitations in the test circuitry. For example, during a typical burn-in test mode, the electronic storage device is placed on a burn-in board and placed in a burn-in oven so that infant-life failures can be detected. During such a burn-in test mode, the electronic storage device will typically enter into an idle state if no activity is detected on the input pins of the electronic storage device after a predetermined period of time (e.g., 30 nanoseconds). This time-out feature is typically beneficially provided to minimize the power consumption of the electronic storage device, and the test circuitry typically has no effect on this time-out feature. That is, the time-out feature typically becomes active regardless of whether the electronic storage device is in burn-in, or any other type of, test mode. However, most test rigs have cycle times on the order of 2000-3000 nanoseconds due to processing limitations and noise considerations, among other things. Thus, the electronic storage device can only be tested for a small percentage of the test rig cycle time (e.g., for {fraction (30/3000)}, or {fraction (1/100)} of the test rig cycle time). Consequently, the electronic storage device may not be thoroughly, or at least efficiently, tested due to limitations in the test circuitry.
In view of the foregoing, it would be desirable to provide test mode circuitry which overcomes the above-stated problems. More particularly, it would be desirable to provide test mode circuitry having a reliable high voltage detection circuit and/or a time-out feature disable circuit for allowing electronic storage, or other, devices to be tested in a more thorough and efficient manner.
According to the present invention, test mode circuitry for electronic storage devices and the like is provided. In a first embodiment, the test mode circuitry includes a detection circuit for detecting a supervoltage on an input connection of an electronic storage device or the like. The detection circuit includes an N-channel transistor having a first source, a first gate, and a first drain, wherein the first gate is connected to the input connection and the first drain is connected to a supply voltage. The detection circuit also includes a P-channel transistor having a second source, a second gate, and a second drain, wherein the second source is connected to the first source and the second gate is connected to a biasing circuit. The biasing circuit can include, for example, a pull-up circuit connected between the second gate and the supply voltage, and a weak load connected between the second gate and ground. The pull-up circuit can be, for example, a P-channel transistor having a gate and drain that are connected to the second gate. The weak load can be, for example, an N-channel transistor having a drain that is connected to the second gate. The second drain provides an output signal for the detection circuit that is indicative of the supervoltage being applied to the input connection.
In accordance with another aspect of the present invention, the detection circuit can include a switching circuit connected to the second gate for biasing the second gate. The switching circuit can be, for example, a P-channel transistor having a drain that is connected to the second gate.
In accordance with a further aspect of the present invention, the detection circuit can include a weak load connected to the second drain for regulating the value of the output signal. The weak load can be, for example, an N-channel transistor having a drain that is connected to the second drain.
In accordance with a still further aspect of the present invention, the detection circuit can include a noise filtering circuit connected to the second drain for filtering the output signal. The noise filtering circuit can be, for example, a schmitt trigger.
In accordance with a still further aspect of the present invention, the N-channel transistor has a substrate, and the substrate can be beneficially connected to the first source or to ground so as to avoid or introduce a body effect, respectively, in the detection circuit.
In accordance with a still further aspect of the present invention, the supervoltage has a first voltage value, the supply voltage has a second voltage value, and the first voltage value is greater than the second voltage value.
In a second embodiment, the test mode circuitry includes a test mode circuit for an electronic storage device having a memory access cycle time-out feature. The test mode circuit incorporates a detection circuit, such as the one described above, and a memory access cycle time-out feature override circuit. The detection circuit detects a supervoltage on an input connection of the electronic storage device and generates an active test mode signal in response thereto. The memory access time-out feature override circuit is responsive to the active test mode signal and overrides the memory access cycle time-out feature and generates an active memory block select signal for substantially all of a memory access cycle of the electronic storage device. The memory access cycle time-out feature override circuit typically includes a long cycle enable circuit that is responsive to the active test mode signal and generates a long cycle enable signal in response thereto. The memory access cycle time-out feature override circuit typically also includes a memory block reset control circuit that is responsive to the long cycle enable signal and generates a memory block reset control signal in response thereto. The memory access cycle time-out feature override circuit typically further includes a memory block select circuit that is responsive to the memory block reset control signal and generates the active memory block select signal in response thereto.